When making a CMOS device that includes metal gate electrodes, a replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed to create a trench between the spacers. The trench is filled with a first metal. A second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal.
Current processes for etching polysilicon layers generate patterned polysilicon layers with side walls that are vertical or slightly inclined such that the lower surface of each patterned layer is wider than the upper surface. Although such a profile may be suitable for processes that retain the patterned polysilicon layers, it may be inappropriate for a replacement gate process, especially when making transistors with 45 nm or smaller gate lengths. After removing such a patterned polysilicon layer, it may be difficult to uniformly coat the sidewalls of the resulting trench with various materials. In addition, it may not be possible to completely fill such a trench with metal, as voids may form at the trench center.
Accordingly, there is a need for an improved method for making a semiconductor device that includes metal gate electrodes. There is a need for a method for generating a patterned polysilicon layer with a profile that is compatible with replacement gate processes for making transistors with very small gate lengths. The present invention provides such a method.
Features shown in these figures are not intended to be drawn to scale.